Introduction

Briefly recap what we've completed so far:

• Converted RTL into a technology-mapped gate-level netlist through synthesis.

• Created the floorplan for physical implementation.

• Placed all the standard cells at their respective locations.

• Analyzed and optimized timing throughout these stages.

However, until now, we have generally assumed an ideal clock.

After placement, all sequential elements have physical locations. We now need to distribute the clock signal from its source to all these sequential elements through an actual physical clock network.

This is where Clock Tree Synthesis (CTS) comes into the picture.

Why Can't We Route the Clock Like an Ordinary Signal?

We might wonder why we cannot simply route the clock net to all sequential elements, just like any other signal.

The reason is that clock distribution has additional challenges related to timing, power, area and signal integrity.

Let's understand them briefly.

1. Implications on Signal Integrity

Signal integrity is particularly important for clock signals because any unwanted disturbance can affect the operation of sequential elements.

Some important concerns include:

• Design Rule Violations

  Clock Tree has to satisfy the Design Rule Constraints:

  • Max Transition limit

  • Max Capacitance limit

  • Max Fanout limit

• Noise and Crosstalk: Coupling from neighboring signals can disturb clock propagation and cause variations in clock arrival times.

• Glitches: Unwanted transitions on the clock signal can potentially cause sequential elements to capture incorrect data.

Clock buffers also need to maintain appropriate rise and fall transition characteristics.

2. Implications on Timing

Two important clock parameters affect timing:

Clock Skew

Clock skew is the difference in clock arrival times at two different sequential elements.

Ideally, the clock should reach all sequential elements simultaneously. However, differences in wire lengths and delays can cause variations in clock arrival times.

Excessive clock skew can affect setup and hold timing.

Clock Insertion Delay

Clock insertion delay is the time taken by the clock signal to travel from the clock source to a sequential element.

The clock network introduces additional delay due to buffers and interconnects. This delay needs to be controlled to meet timing requirements.

3. Implications on Power

The clock network is one of the major contributors to dynamic power consumption in a chip.

This is because: P_dynamic = α × C × V_DD² × f

• The activity factor (α) of the clock network is 200% ! (ie 2 toggles per clock cycle)

• The clock capacitance consists of:

  • Clock generation (i.e., PLL, clock dividers, etc.)

  • Clock elements (buffers, inverters, clock gates)

  • Clock wires

  • Clock load of sequential elements

• Clock networks are huge

Therefore, an unnecessarily large clock network can significantly increase power consumption.

4. Implications on Area

The clock network consists of clock buffers, inverters and interconnects.

• Clock buffers and inverters occupy silicon area.

• Clock wires consume routing resources.

• The clock network must reach sequential elements distributed across the chip.

Therefore, clock distribution requires considerable cell area and routing resources.

This is why we cannot simply route the clock net to all sequential elements, just like any other signal.

3. Goals of CTS

From the above challenges, we can understand that clock distribution must be carefully designed.

The primary goals of CTS are:

1. Minimize Clock Skew: Ensure that the difference in clock arrival times across sequential elements is as small as possible.

2. Meet Target Insertion Delay: Keep clock insertion delay within the specified minimum and maximum limits.

3. Maintain Design Rule Constraints: Ensure that clock signals have transition times within the specified limits.

4. Optimize Power and Area: Build an efficient clock network without excessive buffer insertion, power consumption or routing usage.

5. Maintain Signal Integrity: Ensure reliable clock propagation with minimal noise and unwanted disturbances.

The clock network is constructed by connecting the clock source to all sequential elements through an appropriate distribution network.