Introduction About the Course

In this Physical Design course, you will learn the concepts involved in transforming a synthesized digital design into a physical layout suitable for manufacturing. The course covers the ASIC design flow, Physical Design fundamentals, implementation stages, signoff, and practical design challenges.

Pre-requisites for this course :

• Digital Electronics

• Basic understanding of CMOS circuits

• Basics of Timing Analysis (STA)

Course Structure

Level 1: Introduction

Understanding the ASIC design flow, what Physical Design is, why it is important, and its role in achieving Power, Performance, and Area (PPA) goals.

Level 2: Fundamentals

Introduction to Standard cells and Libaries, ASIC design inputs, technology and design files, and Timing models for standard cells and interconnects.

Level 3: Logic Synthesis

Covers how RTL is mapped to standard cells to produce a gate-level netlist. Introduces common logic and technology-dependent optimizations, clock-gating inference, and the checks and timing, area, and power reports reviewed before Physical Design.

Level 4: Physical Design Implementation

Covers the major implementation stages: Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing, with emphasis on their objectives, optimization, and common design challenges.

Level 5: Physical Verification, Signoff & ECO

Understanding the key physical verification and signoff checks, including DRC, ERC, LVS, LEC, IR drop, EM, antenna checks, and ECO techniques.

Level 6: Scenario-Based & Advanced Concepts

Application of Physical Design concepts through scenario-based questions, along with selected advanced topics such as double patterning and IC fabrication fundamentals.

Level 7: Projects

Hands-on application of the concepts through practical RTL-to-GDSII projects. Projects will cover complete physical implementation flows, hierarchical design, architectural comparisons for PPA, and low-power implementation techniques. Additional projects will be introduced to provide exposure to different design challenges, architectures, and optimization techniques.