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Questions
1

Spare cell

2

Total Path Delay

3

Cell Placement and Power Integrity

4

Placement Congestion vs. IR Drop

5

Hold Timing

6

Placement Optimization – Setup Timing

7

Cell Clustering and Power

8

Timing vs. Placement Tradeoff

9

Dynamic IR drop

10

Data Path Pruning

11

Tap cell & Power switch

12

Tap-cell spacing

13

Power gated domain

14

Static IR passes, dynamic IR fails

15

Static IR drop

16

Wire length vs Timing

17

Placement halo

18

Pin accessibility

19

Core-area estimation

20

Low utilization, severe congestion

21

Effect of Cell Upsizing

22

Bilinear interpolation

23

Standard Cell Height

24

Rectangles

25

Vowels Together

26

Cache Tag Size

27

Logic Inference

28

Synthesis Optimization

29

Technology Mapping

30

Unresolved module

31

RTL Inference

32

Synthesis Output

33

Setup Timing - Fix

34

Physical Design - Inputs

35

SPEF File

36

Standard Cell Location

37

Libs File

38

DEF & GDSII

39

Fabrication Process

40

Gate-Level Netlist

41

Logic Synthesis Output

42

Architecture Design

43

Aptitude - Clock Synchronization Puzzle

44

Physical Design Technique

45

Setup Slack Calculation With Jitter

46

Clock Domain Crossing - 2

47

Multi Core Cache Coherence

48

Direct-Mapped Address Field

49

Mealy FSM Sequence Detector

50

Digital Design - Inverter

51

Metastability Window

52

Setup Slack3

53

Transistor Condition

54

Max Frequency2

55

Data Hazard

56

Differential Pair Vs Single Ended Amplifier

57

D-Flip Flop Count

58

Divider Logic

59

Routing Congestion and Track Assignment

60

CTS - Optimization

61

Hold Time Violation with Clock Skew

62

Setup Slack with On-Chip Variation (OCV)

63

Multi Bit Synchronization

64

FSM Bubble State Elimination

65

Memory Hierarchy and Page Table Walk

66

Cache Coherency and Bandwidth

67

UVM - Connect Phase

68

UVM - Phases

69

UVM - top down phases

70

UVM - connect_phase()

71

System Verilog Looping (Overflow/Rollover Concept)

72

System Verilog - class operators

73

CMOS Pass Transistor

74

Verilog: System Tasks

75

SystemVerilog Combination Logic Modelling

76

Clock Generation

77

CMOS Power

78

Sequential Logic : Race-Condition

79

CMOS Device Physics

80

Verilog Procedural Assignments

81

Setup and Hold

82

Sequence Generator

83

Via Resistance and Yield Optimization

84

Electromigration Limits

85

Randomization Constraints

86

Crosstalk Induced Delay

87

ICG Timing

88

Effective Bandwidth

89

TLB Tag Width

90

Area Trade Off

91

Worst Setup Slack

92

Scan Shift Power Budgeting

93

Antenna Effect Limits

94

Clock Tree Network Power

95

Data Transfer Latency

96

Hex Sequence

97

Clock Edge Synchronization

98

Physical Design Issue

99

Write Buffer

100

Current Mirror2

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