Data Path Pruning

A design contains the following RTL:

reg [15:0] result;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        result <= 16'b0;
    else if (enable)
        result <= a * b;
end

assign done = enable;

Assume that a and b are 8-bit unsigned inputs. The register result is not connected to any output or other logic, and no preservation attributes are applied.

After synthesis, the engineer finds that both the multiplier and the result register have disappeared. What is the best explanation?